SiLab С8051F34x datasheet: различия между версиями
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Строка 430:
<span title="The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop software. The MCU family has a superset of all the peripherals included with a standard 8051. Included are four 16-bit counter/timers (see description in Section 21), an enhanced full-duplex UART (see description in Section 18), an Enhanced SPI (see description in Section 20), 256 bytes of internal RAM, 128 byte Special Function Register (SFR) address space (Section 9.2.6), and 25 Port I/O (see description in Section 15). The CIP-51 also includes on-chip debug hardware (see description in Section 23), and interfaces directly with the analog and digital subsystems providing a complete data acquisition or control-system solution in a single integrated circuit.">
Ядро микропроцессорного устройства управления (microprocessor control unit, MCU) представляет
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Строка 666:
| DPH
| <span title="The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indirectly addressed memory.">
Старший байт указателя данных. Регистр DPL представляет
| C8051F340.h
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Строка 672:
| DPL
| <span title="The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indirectly addressed memory.">
Младший байт указателя данных. Регистр DPL представляет
| C8051F340.h
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Строка 2256:
<span title="Timer 2 is a 16-bit timer formed by two 8-bit SFRs: TMR2L (low byte) and TMR2H (high byte). Timer 2 may operate in 16-bit auto-reload mode, (split) 8-bit auto-reload mode, USB Start-of-Frame (SOF) capture mode, or Low-Frequency Oscillator (LFO) Falling Edge capture mode. The Timer 2 operation mode is defined by the T2SPLIT (TMR2CN.3), T2CE (TMR2CN.4) bits, and T2CSS (TMR2CN.1) bits.">
<tt>Timer 2</tt> представляет
</span>
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